1. Field of the Invention
The present invention relates to an image sensor, a data output method, an image pickup device, and a camera and, more particularly, to an image sensor, a data output method, an image pickup device, and a camera that are configured to output the information associated with image sensor processing at high speeds without involving a large-scale increase in the size of circuitry.
2. Description of the Related Art
An image pickup device for taking images has an image sensor for outputting image data obtained by photoelectric conversion, such as a CMOS (Complementary Metal Oxide Semiconductor) sensor or the like and a processor for processing the image data, such as a DSP (Digital Signal Processor) or the like, for example.
With the CMOS sensor, image data is outputted (or transmitted) by parallel output to an external DSP, thereby enhancing the transmission efficiency of image data (refer to Japanese Patent Laid-open No. 2008-048313 for example).
Also, the CMOS sensor incorporates a register group configured to store the information inside the CMOS sensor.
The information internal to the CMOS sensor includes various kinds of information associated with the processing that is executed inside the CMOS sensor. The information associated with the processing that is executed inside the CMOS information includes the information for determining the processing that is executed inside the CMOS sensor, such as gain information that is a gain of image data, namely, the information about the amplification rate with which image data is amplified by the CMOS sensor and operation mode information indicative of CMOS sensor operation modes, for example.
The external DSP writes and reads values (hereafter also referred to as a register value group) stored in the register group incorporated in the CMOS sensor in order to monitor and control the CMOS sensor.
To be more specific, the CMOS sensor has a parallel I/F (Interface) configured to output image data in parallel output and a serial I/F configured to execute serial communication, such as two-wire serial communication or three-wire serial communication, with the outside for reading and writing the register value group.
Then, in the CMOS sensor, register value group write and read operations with the DSP are executed in serial communication via the serial I/F.
A CMOS sensor for reading an external register value group in an echoback scheme is known.
In the echoback scheme, when a register value group is written to the CMOS sensor, the register value group so far stored in the register group is outputted from the CMOS sensor in a serial output manner (or echobacked).
It should be noted that, in the echoback scheme, if no write operation to the register group is executed, no register value group is outputted, so that, in order to read the register value group, a proper value must be written to the register group.
Now, referring to FIG. 1, there is shown a block diagram illustrating an exemplary configuration of a related-art image pickup device.
As shown in FIG. 1, an image pickup device has a CMOS sensor 10 and a DSP 20. The CMOS sensor 10 and the DSP 20 are interconnected by both a parallel output line 30 and a serial communication line 40.
The CMOS sensor 10 has a pixel array block 11, a parallel I/F 12, a register group 13, and a serial I/F 14.
The pixel array block 11 has pixels as photoelectric conversion elements arranged in a matrix to photoelectrically convert the light projected thereto, thereby getting image data as an electrical signal.
Image data outputted from the pixel array block 11 is of a Bayer arrangement in which each pixel has one of color signals R (Red), G (Green), and B (Blue) as a pixel value. Namely, the arrangement of the pixels (or color filters not shown) of the pixel array block 11 is of the Bayer arrangement.
The pixel value of each pixel as the image data obtained by the pixel array block 11 is fast outputted to the parallel I/F 12 via a 10-bit parallel bus and an 8-channel serial bus, for example.
The parallel I/F 12 receives the image data from the pixel array block 11 and outputs the received image data to the outside of the CMOS sensor 10, namely, the external DSP 20 in this case in parallel output.
It should be noted that the parallel I/F 12 and the DSP 20 are interconnected by the parallel output line 30.
The parallel output line 30 has an image data output line 31 and a parallel clock line 32.
The image data output line 31 is 12 signal lines of LVDS (Low Voltage Differential Signaling), for example. The parallel I/F 12 transmits (or outputs) the pixel value of each pixel as image data to the DSP 20 in parallel output via the image data output line 31 by a differential signal having an amplitude of several 100 mV to approx. 350 mV.
The parallel clock line 32 is a signal line for transmitting a clock of 480 MHz of LVDS, for example. The parallel I/F 12 supplies (or outputs) the clock of 480 MHz of LVDS to the DSP 20 via the parallel clock line 32.
The DSP 20 receives the image data transmitted via the image data output line 31, in synchronization with a clock supplied via the parallel clock line 32, and executes necessary processing on the received image data, outputting the processed image data. The processing to be executed by the DSP 20 includes hand-shake cancellation and image data dynamic range expansion, for example.
On the other hand, in the CMOS sensor 10, the register group 13 stores information internal to the CMOS sensor 10.
Writing a register value (group) to the register group 13 is executed by the CMOS sensor 10 itself without an instruction from the outside or in accordance with an instruction given from the outside.
Namely, the CMOS sensor 10 writes OPB (OPtical Black) information indicative of an optical black level that is provided when image data is obtained by photoelectric conversion to the register group 13, for example.
Also, the register group 13 stores gain information in accordance with an instruction given from the external DSP 20, for example.
The information (or the register value group) stored in the register group 13 is referenced as demanded inside the CMOS sensor 10 to be used for determining processing (or contents thereof) to be executed in the CMOS sensor 10, for example. Namely, in the pixel array block 11, the image data is multiplied by a gain indicated by gain information stored in the register group 13, for example.
Also, the information stored in the register group 13 is read by the external DSP 20 as demanded.
Writing or reading information supplied from the external DSP 20 to or from the register group 13 is executed via the serial I/F 14.
Namely, the serial I/F 14 and the DSP 20 are interconnected by the serial communication line 40.
The serial communication line 40 is a signal line for executing 3-wire serial communication and has a register write line 41, a register read line 42, and a serial clock line 43.
The register write line 41 is a signal line that is used for writing information from the outside to the register group 13. The DSP 20 transmits the information to be written to the register group 13 to the serial I/F 14 in serial communication via the register write line 41, the serial I/F 14 receives the signal transmitted from the DSP 20 via the register write line 41 and writes the received signal to the register group 13.
The register read line 42 is a signal line that is used for reading information (or a register value group) stored in the register group 13 to the outside. When a register value (group) is requested by the DSP 20 via the serial communication line 40, the serial I/F 14 reads the requested register value group from the register group 13 and transmits the register value group to the DSP 20 via the register read line 42.
The serial clock line 43 is a signal line that is used for transmitting the clock for passing register value groups between the serial I/F 14 and the DSP 20 via the register write line 41 and the register read line 42. The external DSP 20 supplies (or outputs) a clock of several kHz to several 10 MHz to the serial I/F 14 via the serial clock line 43.
The passing of register value groups between the serial I/F 14 and the DSP 20 is executed in synchronization with the clock on the serial clock line 43.